Power converters form the ubiquitous base of most electrical products and systems. A fundamental requirement of the power converter is high power conversion efficiency, measured as the division of output power by input power.
FIG. A1, FIG. A4 and FIG. A5 illustrate a prior art pulse width modulation (PWM)-pulse frequency modulation (PFM) dual mode modulator 1 together with some of its performance characteristics like power conversion efficiency (FIG. A4) and dynamic load regulation following a large step increase of its load current (FIG. A5). The prior art PWM-PFM dual mode modulator 1 converts power from an unregulated supply voltage VIN then delivers, through a power output stage 2, a regulated output voltage VOUT with a load current ILOAD through an external LOAD (not shown) to a power ground PGND. The power output stage 2 has a number of high-side and low-side switching power transistors, joined at a switching voltage node V(Lx), to deliver the required load current ILOAD at the output voltage VOUT. The power output stage 2 also senses and provides the output voltage VOUT and the load current ILOAD to the prior art PWM-PFM dual mode modulator 1 to enable its proper regulation of the output voltage VOUT.
Notice that the prior art PWM-PFM dual mode modulator 1 can selectively activate a PFM modulator 30 or a PWM modulator 10 to effect the output voltage regulation. While the internal details of both the PFM modulator 30 and the PWM modulator 10 are known to those skilled in the art, it is nevertheless worthwhile to point out that the PWM modulator 10 has a PWM-feedback control loop 11 with an error amplifier (E/A) circuit 12 in it. As a result, the PWM-loop response speed tracks the slew rate of the E/A.
Turning now to FIG. A2 and FIG. A3 that respectively depicts the internal power loss vs. load current ILOAD characteristics of a fixed frequency converter and a variable frequency converter. As examples, the PWM modulator 10 is a fixed frequency converter while the PFM modulator 30 is a variable frequency converter. The total internal modulator power loss has three components: switching loss, conduction loss and fixed loss. In a fixed frequency converter the switching loss stays constant with ILOAD while the switching loss in a variable frequency converter is proportional to ILOAD. For both types of converters the conduction loss and the fixed loss are about the same with the conduction loss being proportional to the ILOAD while the fixed loss is insignificant in these examples. As a result, under the condition of increasingly high ILOAD the modulator power loss of a PWM modulator becomes increasingly less than that of a PFM modulator while under diminishingly low ILOAD the opposite is true. Therefore, as illustrated with an example in FIG. A4, under low ILOAD (e.g., when a laptop is on standby) the prior art PWM-PFM dual mode modulator 1 would power its PFM modulator 30 to drive the power output stage 2 in a PFM mode while leaving its PWM modulator 10 in a power off state to save energy. On the other hand, under high ILOAD the prior art PWM-PFM dual mode modulator 1 would power its PWM modulator 10 instead to drive the power output stage 2 in a PWM mode while leaving its PFM modulator 30 in a power off state to save energy. In this way, the prior art PWM-PFM dual mode modulator 1 would achieve a high power conversion efficiency throughout the range of ILOAD (solid curve of FIG. A4). In addition, PWM is a popular standard and many applications are designed to operate in the PWM mode. However, if the prior art PWM-PFM dual mode modulator 1 were to always operate in a PWM mode throughout the range of ILOAD, it would suffer from increasingly lower power conversion efficiency below an ILOAD˜160 mA (dashed curve of FIG. A4).
As another performance characteristic of the prior art PWM-PFM dual mode modulator 1, FIG. A5 shows an example of its dynamic load regulation following a large step increase of its ILOAD (0-300 mA at time t0). Prior to time t0 the prior art PWM-PFM dual mode modulator 1 has been operating under a normal PFM mode. Between time t0 and time t3 the prior art PWM-PFM dual mode modulator 1 has to quickly power off its PFM modulator 30, power on then start up its PWM modulator 10 till it settles in a normal PWM mode again at time t3. As the PWM modulator 10 needs time to power on and start up its operation (see the V(Lx) vs. time plot through t0, t1 and t2), the output voltage VOUT(t) has meanwhile suffered from a substantial transient dip of as much as ˜300 mV at time t2 from its normal regulated level of 1.8 V. While this VOUT(t) dip only lasts for about 30 microseconds it may not be acceptable to many sensitive electronic devices powered by it. Therefore, there exists a need to substantially improve the dynamic load regulation of a prior art PWM-PFM dual mode modulator 1 by reducing the VOUT(t) dip and shortening its PFM-to-PWM mode transition period.